This application is based on and claims the benefit of priority from the prior Japanese Paten Application No. 2002-099061, filed on Apr. 1, 2002, the entire contents of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device with a high-speed performance.
2. Description of Related Art
Information process systems having an LSI chip, e.g., semiconductor memory, mounted on a print circuit board (PCB) are increasingly improved to have a high-speed performance. When the signal frequency utilized in such systems reaches to 1 GHz, further to 10 GHz. electric signals transmitted on the signal lines on the PCB become signal waves (i.e., electromagnetic waves), and signal reflection at a signal input terminal becomes a subject to be solved. In detail, interference between an advancing wave and a retrograding wave causes a signal to be ringing. As a result, there is a fear that the LSI chip fails to distinguish the input signal.
To prevent the LSI chip from signal wave reflecting at the signal input terminal, it is required to dispose a resistive terminator, i.e., to connect a terminating resistor whose impedance is matched with a characteristic impedance of the signal line. However, if a termination resistor is disposed at a transmission line, static current flows therein. Therefore, the system will consume waste power.
Another approach is to dispose a switch device between the termination resistor and the transmission line so as to selectively cause it on only when signals are transmitted. However, this also is impossible to perfectively reduce the waste power consumption. Therefore, it is required for a driving circuit of the LSI chip to have large drivability.
A semiconductor integrated circuit device having an input buffer connected to an input terminal, comprises:
a transfer gate one node of which is connected to the input terminal and the other node to an internal circuit, the transfer gate being on in an ordinary state;
a transmission line connected to the other node of the transfer gate; and
a control circuit configured to detect level transition of an Input signal on the input terminal and drive to turn off the transfer gate after the input signal is transferred through the transfer gate and before a lapse of while the input signal makes a round trip on the transmission line.